Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on.Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a.Virtex-4 (WARP FPGA Board v2.2): OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip (87MB).
Xilinx ise 10.1 registration id free pro#
Virtex-II Pro (WARP FPGA Board v1.2): OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip (87 MB).This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.). The code and models for this design correspond to svn rev 1400. Updated warpphy/warpmac to reflect changes to registers in the PHY.Added support for the WARPnet Measurement Framework, including a new top-level application (WARPNET_EXAMPLE).Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources.Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row.Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions).Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing.